How does the Remote Update IP work?

We have been trying to implement a similar solution in one of our projects and have observed the same problem. In our case, the FPGA is configured in DTA mode and we have a simple FSM that reads the Reconfiguration Trigger Conditions to determine what caused the reconfiguration. The FSM essential only has 3 states that are performed when reset is de-asserted:

1. Wait for the busy signal to be de-asserted

2. Wait for 4 clocks (inherited from an old design)

3. Read the Reconfiguration Trigger Conditions register

However, the register was always returning 0x1f, in the exact same way as described in this post. Eventually, we discovered that the IP requires some initialisation time after the busy signal is de-asserted for the first time. By waiting for 1ms after the busy signal goes low, we were able to read the register. The updated FSM still only has 3 states that are performed when reset is de-asserted:

1. Wait for the busy signal to be de-asserted

2. Wait for 1 ms

3. Read the Reconfiguration Trigger Conditions

It's worth pointing out that the 1ms figure was reached after trial and error, as this initialisation time isn't documented it's not clear how long the delay actually needs to be.

As this is an old post, I guess the original poster has solved this problem. However, this has proven to be a bit of a time sink for us so I'm posting this solution in case anyone else has this same issue.