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In my case I have 4 LVDS data channels (A0-A3) and the dedicated CLK channel.
Each of these data channels has 7 bits therfore 28bits. (8xR, 8xG, 8xB + 1x hsync, 1x vsync, 1x DataEnable (DE) and 1x NA)
I configured my ALTLVDS_RX with 4 channels and 7 for the deserialization factor. Consequential i have 28 output signals RX_OUT[27..0].
The problem is that I don't know which of these signals belongs to which output signals.
Is there a documentation how the deserializer assigns the bits to the output signals?
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Search for 'rx_channel_data_align' in the LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide. In particular, take a look at the following:
- Page 2-13 (page 15) which describes how you manually align the bits
- Page 3-8 (page 36) which describes this process in more detail.
I was a bit surprised when first encountering this years ago, having become used to commercial Camera Link parts which lock on and define bits relative to the input clock (not the higher speed bit clock).
Kevin Jennings
Honored Contributor
