How does altlvds make bit alignment?

In my case I have 4 LVDS data channels (A0-A3) and the dedicated CLK channel.

Each of these data channels has 7 bits therfore 28bits. (8xR, 8xG, 8xB + 1x hsync, 1x vsync, 1x DataEnable (DE) and 1x NA)

I configured my ALTLVDS_RX with 4 channels and 7 for the deserialization factor. Consequential i have 28 output signals RX_OUT[27..0].

The problem is that I don't know which of these signals belongs to which output signals.

Is there a documentation how the deserializer assigns the bits to the output signals?

http://i41.tinypic.com/33le2vt.jpg