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Altera_Forum
Honored Contributor
Honored ContributorHow do I create AXI3 interface to DDR3 SDRAM Controller with UniPHY?
Hello, I am trying to port an old design to the Arria V GX Starter Kit development board. The old design had a 64-bit AXI3 interface to a custom DDR2 controller but now I need to port it to th...
Altera_ForumHonored Contributor
Honored Contributorok i see. as mentioned, I haven't used any of the AXI Agents, just the Hard Processor System
you can't use a bus internally in Qsys and also export it. maybe the AXI Translator is what you need. connect the AXI Master to the MM Slave, and export the AXI Slave
