How do I create AXI3 interface to DDR3 SDRAM Controller with UniPHY?

Thanks for the tip about the slave but that didn't work either (see attached JPEG). I instantiated the AXI slave and connected its master interface to the Avalon MM port on the DDR3 controller. However, I am not able to export the AXI interface to my external logic so it can talk to the controller. If I click on the "HDL Example" tab in Qsys, I don't see an AXI interface that my logic can connect to. If I try exporting the AXI master interface, then the thick, black line that connects the slave's AXI master interface to the DDR3 controller's Avalon interface goes away.