How do I configure an I/O BAR in Cyclone IV GX PCIe core?

I'm using a Cyclone IV GX FPGA and take advantage of the contained PCIe hard IP. In order to get around a cache issue, I would like to configure an I/O BAR instead of a memory BAR. However, I cannot spot a possibility to configure this in the PCIe Compiler in Platform Designer (18.1).

• Does Cyclone IV GX support I/O BAR implementation?
• If yes, how can I configure that?

Thanks for your inputs.