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MS
New Contributor
New ContributorHow do I configure an I/O BAR in Cyclone IV GX PCIe core?
I'm using a Cyclone IV GX FPGA and take advantage of the contained PCIe hard IP. In order to get around a cache issue, I would like to configure an I/O BAR instead of a memory BAR. However, I cannot ...
MSNew Contributor
New ContributorHi Nathan,
Thanks for your answer. Reading the indicated section (p 37/370) I learned that I need to distinguish between IP generated by QSYS vs the IP Compiler. In the later one I/O BARs are accessible when choosing a legacy endpoint implementation instead of the native one.
Best wishes,
MS
