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Altera_Forum
Honored Contributor
14 years agoFirstly, generate a stream using test pattern generator(8 or 10bit stream + 27MHz clk + data valid signal), then use SDI megacore to generate SDI output. It requires 27MHz input clock (You must use the same as for the video parallel stream mentioned before) + 270MHz reference clock from the PLL of the 27MHz (ratio 10/1), if You're trying to generate SD SDI.