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Hello!everybody!
I am a begginner of dspbuilder, I have lerned it for one month and I like it. Recently I met some problems and I want to ask for some advise.Thank you!
My question is when I design a model that need to use the negedge of the base clock to trigger the filt-flop, how can I realized it ? I have read the dsobuilder's user guide and
not find the answer. It seemingly that only the rising edge of the base clock ,derived clock and the pll clock can be used. I am not sure if all data change at the rising edge,
wheather it could cause a timing competition? Or there are some hidden method in dspbuilder to avoid this happening？
Thank you for your patience to read over my question,if you have some ideal,please teach me,Thanks!
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When I use dspbuilder I don't care how it implements the design as the code is machine code and it is not meant to be edited but used straight away.
The tool takes care of timing. So in short you don't need this clock edge choice. If it does not meet timing then one way is to add registers manually or redesign or increase clock margin.
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