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Altera_Forum's avatar
Altera_Forum
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17 years ago

How Can I set up DMA operation with my own PC software application?

Hi All:

I want to re-use the pcie_highperformancedesign example provided by the Arria GX Development Kit. Now I am confused with the PC software application altpcie_demo.exe. :confused:

I am trying to control FPGA to initiate dma read and write operation just like altpcie_demo does with my own PC software application but failed.

Firstly, I used Jungo Windriver to generate a pcie driver. With the API functions provided by the driver I can access(R/W) configure registers ,memory bar 1:0(the syncram) and bar2(dma control registers).

Secondly, I creat a Read Descriptor Table--Header+2 Descriptors and set data(Length,Ep mem addr, RC mem addr)for desciptors. The header has four dw(DW0,DW1,DW2,DW3). For DMA Read, I set DW0=0x00040002,DW1=0,DW2=addr of header,DW3=0x1. Then I write DW0 to Bar2+0x10,DW1 to Bar2+0x14,DW2 to Bar2+0x18,DW3 to Bar2+0x1c.

My first question: Where(mem addr) can I poll the RCLast value to indicate the completion of DMA read?:confused:

Thirdly, I want to transfer the DMA Read data back to PC. I creat a Write Descriptor Table--Header+2 Descriptors.In each descriptor, I set PC mem addr for write back data and addr of EP mem correctly .The header has four dw(DW0-DW3). For DMA Write, I set DW0=0x00050002,DW1=0,DW2=addr of Header,DW3=0x1. Then I write DW0 to Bar2+0x0,DW1 to Bar2+0x4,DW2 to Bar2+0x8,DW3 to Bar2+0xc.

At the end, I checked the write back data and found that the write back data are all zeros.It seems like that the FPGA does nothing at all.:confused:

What are the detailed steps I should follow to set up the DMA operation correctly? I read the pci express compiler doc but didn't get enough information about software application.

Thanks a lot for any help.

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Brett,

    You are right. The first step(writing 0xffff to DW0)will reset the DMA and last

    step(writing to DW3) will start the DMA. But i am seeing some issue with write_dma read address to end point memory in RTL. The address goes beyond the length specified in descriptor. It looks ok with read DMA. Has anybody observed same and tested at higher level ?.

    Thanks

    Sharan
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    The extra read address to end point memory is not an issue during dma write. data from end point memory is written to local fifo and only exact size is read from fifo. fifo is cleared at the end of transfer.

    But when i disabled the dma read and enable only dma write in root complex BFM driver(inside chained_dma_test task), the 2nd tranfer is stuck in the middle as tx_st_ready from pci core is asserted and test fails with timeout error.

    it works only if dma read is also enabled. in our application, we don't need the dma read operation. please help..

    thanks.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    I am trying to write a pci driver code to write and read data in to the kernel space..

    while i am reading back i am not getting the actual data, sometimes getting segmentation problem. I wanted to know what is maximum memory we can allocate using pci_alloc_consistent().