Forum Discussion
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- Hello Hey Hey, Thank you for your response, that was very informative and cleared up a lot. I have atleast one more point of confusion. There are two Chaining DMA Descriptor Headers at offset 0x00 and 0x10. The first for write and the other for read. Why is there a Direction bit in the Control Fields (Table 7-4 of PCI Express Compilers Users Guide 8.0)? Is this a redudant thing, or is there some significance to this bit. To me, I would assume the registers at 0x00 and 0x10 specify the direction. Thanks. --- Quote End --- I am little confused about above post. It says descriptor headers is at offset 0x00 and 0x10 where as Table 4-9 in compiler guide show that 0x00 holds device/vendor ID. Any help to clarify is appreciated