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Altera_Forum
Honored Contributor
17 years agoI am correct that DMA operates on the End Point memory mapped to BAR[0], or is the memory involved in DMA located elsewhere?
Also, for individual DWORD read/writes to RC_SLAVE memory, must I set USE_RC_DIRECT_MEM to 1? altpcierd_rc_slave.vhd: USE_EP_MWR := 0;-- Allow EP to issue MemWr to RC on command USE_RC_MWR_MRD := 1; -- Allow RC access to EP MEM thru opcode regs USE_INIT_MEM: INTEGER := 0; USE_RC_DIRECT_MEM: INTEGER := 0;-- Allow RC direct access to EP MEM USE_EP_IO_RDWR:= 0; -- Allow EP to issue IO Rd/Wr to RC on command Thanks for any insights.