Forum Discussion
I have now done a config loop of the MAC and then I read some of the registers out and display them on the LEDs. For some reason TX_ENA is the only one cleared i.e. it is set to '0' which for some unknown reason is the value activating the LEDs on my PCIe dev. board. I now guess this is because the TX clock is not set as it should be. I tried to understand from the documentation how it should be and my idea now is to introduce a PLL which creates a 125MHz clk from the 100MHz input clk. I have tried to find information about this but I can't find any hints about it in this forum. If I look at the data path ref. design which is using SFP instead of "regular" PHY it seams to use some 83.3333... clk which seams odd to me, this must be a different PHY i guess since the "regular" PHY uses 125MHz in "plain GigE" setup. Can anyone describe this clocking issue to me i.e. do I need this PLL to set the clock right.
wbr, P-A