How can I get data from Altera Triple Speed Ethernet (TSE) MAC through Avalon bus?

Hi!

Thanks for reply:

General concerns:

- HW pin mapping, the names of the TSE "signals" and the pin mapping of the PCIe dev. board is not 1 to 1. For example I have mapped GM_RX_DV to PIN_E28 which is enet_rx_dv in the board ref. manual.

- The ref. clk of 125MHz in TSE manual is connected to gtx_clk and to tx_clk. Im not sure if I should map it to pin b33 which is enet_gtx_clk or if I can use the same as rx_clk i.e. enet_rx_clk pin M27 (actually signal is "connected" in VHDL i.e. tx_clk <= rx_clk)

- THe rest of my system uses PIN_A20 for clk, I believe it's around 150MHz. Im not sure if it's ok, but I guess it's a different clock domain.

1. I set the mac in the following way

constant mac: std_logic_vector(47 downto 0) := X"861D33B91900";

...

mm_writedata <=mac(31 downto 0);

...

mm_writedata(15 downto 0) <=mac(47 downto 32);

The Command-Config reg:

constant tx_ena: integer := 0;

constant rx_ena: integer := 1;

constant promise_en: integer := 4;

constant tx_addr_ins: integer := 9;

constant rx_err_disc: integer := 26;

...

cc_reg(tx_ena) <='1';

cc_reg(rx_ena) <='1';

cc_reg(promise_en) <='1';

cc_reg(tx_addr_ins) <='1';

cc_reg(rx_err_disc) <='1';

...

write the next cycle.

I'm not sure I understand "Tight the sw reset bit to a LED" I guess i set it with a write <='1', writedata<=... towards avalon-mm then I need to read it once and check if it is still "1". If it is the reset has not "passed" then something is wrong or?

I have set set_1000<='1'; which I guess hard codes the GBit "way". After a PHY reset the 1000 led is shown on the card so I guess the PHY is aligned but I'm not sure what will happend if I connect a 10/100 device.

If needed I can send you my small "project" if it is easier for you too check but I will try to have a look at the reset bit and the stat. regs. I attached the pin file for review.