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  • Altera_Forum's avatar
    Altera_Forum
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    what part are you stuck on in the HIL Design Flow from Volume 2 Section 5?

  • Altera_Forum's avatar
    Altera_Forum
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    The fourth step to replace the functional blocks with a HIL block. After we compile using signal compiler we need to create another simulink model same as the previous but just the functional blocks replaced with HIL block. In the tutorial a simulink model freqsweep_HIL.mdl was provided. My question is how were the functional blocks replaced by a HIL block. To be more specific when you take the HIL block from the simulink library it doesn't have any input and output ports. How does the HIL block get its input and output ports.

  • Altera_Forum's avatar
    Altera_Forum
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    you double click the HIL block, then select the Quartus II project created by Signal Compiler. follow the configuration and it will generate a new block with proper ports