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Altera_Forum's avatar
Altera_Forum
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15 years ago

Hil

I have a pipeline fft model that I want to run on a Stratix III FPGA using HIL. I am attaching a screenshot of my models with and without HIL blocks and the HIL configuration. Now I have the HIL conf...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

In the clock it was low while in the signal block and HIL config it was high. So changed the clock to high