Hi, it is not possible to connecte an onchip memoy (with ECC enabled) to the avalon data master or avalon instruction master bus of the NIOSII system through the avalon interconnect ?

Hi,

I try to generate a NIOSII system with the following configuration using Quatus v17.1:

• NIOSII gen2 processour (reset vector and exception vector addresses are located in the onchip memory)
• Onchip memory: (data width = 32 bits and ECC = enabled, So the data width becames = 39 bits )
• JATG UART

When I started the generation of the HDL files on the Platform Designer, I got the following errors :

Any advice please ?