Hi, it is not possible to connecte an onchip memoy (with ECC enabled) to the avalon data master or avalon instruction master bus of the NIOSII system through the avalon interconnect ?

Hi, I try to generate a NIOSII system with the following configuration using Quatus v17.1: NIOSII gen2 processour (reset vector and exception vector addresses are located in the onchip memory) On...