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Altera_Forum
Honored Contributor
Honored ContributorHELP!!!Question about Avalon MM Slave Template Use
hi, I'm trying to have a coprocessor (that I built in Verilog and want to deploy on a FPGA) interact with a Nios II Processor System. By now I used the Altera Avalon MM Slave template so I can expose...
Altera_ForumHonored Contributor
Honored ContributorLooking at the files there are spaces between each register bank (since each bank supports different access types). Just use the offsets that come in the include file directory of the IP, then you won't need to do the low level addresses.
