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Altera_Forum's avatar
Altera_Forum
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16 years ago

Help!!!IIR Filter design problem

Problem explanation:

Here I am trying to use 2 fir filter to get an iir filter, however, in the feedback loop fir,I got 10 latency, is anyone can help me to reduce the latency and also tell me which latency it is, system clockrate delay or sample rate delay?

and I also have no idea about how to use the system clock in the simulink environment. Everytime if I set my clockrate different from my samplerate, the simulation cant be done.

Also, if I made a design like this by using the primitive block, the system always ask me to add 5 extra delays...

Is there anyone can help? many thanks first!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You should revisit the maths I think ... and think seriously about the relationship between processing clocks and sample rate clocks. In my opinion it would be better for you to actually implement the iir directly - it is three simple equations to represent a biquadratic.