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Alexander_M_Intel's avatar
Alexander_M_Intel
Icon for New Contributor rankNew Contributor
7 years ago

Help with pin assignments involving triple speed ethernet (Cyclone V GT Development Board).

From what I currently see, I would think that I have to manually assign pins for several dozen input/output wires. I have looked at multiple reference guides, but as I am new to Quartus, a good deal of the information is beyond my current understanding.

In essence, I would like to know if there is a simple way to connect the generated ip such that I can stream some data from the Ethernet cable to some core logic I have yet to implement.

I am using Quartus 18.0 and I pull the Triple Ethernet Design from the IP Catalog, using the default settings currently.

One more thing, after reading https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/ug_megafunction_overview.pdf and referring to the diagram on page 8, I was lead to believe there should be some form of <name>_inst.v file that serves as an instantiation template, but I did not see such a file anywhere after generating the ip. Is this a bug?

Best Regards, Alex

2 Replies

  • AnandRaj_S_Intel's avatar
    AnandRaj_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    1. Pin assignment can be done manually or automate using tcl file.
    • generate tcl file using from projects->generate tcl file for project
      • manually key in the pins example " set_location_assignment PIN_5 -to clk_clk"

    2. You can check in the <project directory>\ <qsys directory>\<name>_inst.<v or vhd>" file can be found.

    Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

    Best Regards,

    Anand Raj Shankar

    (This message was posted on behalf of Intel Corporation)

  • Alexander_M_Intel's avatar
    Alexander_M_Intel
    Icon for New Contributor rankNew Contributor
    7 years ago

    Hello Anand, thank you for your quick reply.

    1.)

    I generated a tcl file for the project as per your suggestion and after compiling, I back-annotated the pin assignments so that I could view them in Assignment Editor. The project compiles and writes to the board successfully.

    The display on the board shows a valid IP address

    (This is where the good news ends)

    2.)

    Again, there is no such <name>_inst.v (I'm using verilog) file. I am running Ubuntu 16.04 and I executed $find . -name "*inst*"

    There are 0 files in my project directory or any subdirectories with the string "inst" in the name.

    3.)

    While I have a design on the Cyclone V, I would expect one of the 3 indicator LEDs for the Ethernet connection speed to be lit, but all are dim. In my case, the board is connected properly through the Ethernet port (It shows the 100 megabit LED as lit with the factory default image and I have used the Board Update Portal in the past).

    If possible, could you explain what I should connect these LEDs to? Or tell me if this sounds as though something is invalid? I don't know how much Quartus can do automatically. I just tried to instantiate the module in my project's top level verilog file (without any of my own logic) based on what I saw from the top level verilog file auto generated with the triple speed Ethernet IP.

    Here's some information about my setup. Let me know if there is something else you need.

    IP core: Triple-Speed Ethernet Intel FPGA IP

    Variation: 10/100/1000Mb Ethernet Mac with 1000 BASE-X/SGMII PCS

    All Other Parameters: EVERYTHING IS THE DEFAULT

    Distribution: Ubuntu 16.04

    Quartus Prime Version: 18.0

    FPGA Board: Cyclone V GT Development Kit

    Programming Method: USB Blaster II

    Best Regards, Alex