Forum Discussion
Hello Anand, thank you for your quick reply.
1.)
I generated a tcl file for the project as per your suggestion and after compiling, I back-annotated the pin assignments so that I could view them in Assignment Editor. The project compiles and writes to the board successfully.
The display on the board shows a valid IP address
(This is where the good news ends)
2.)
Again, there is no such <name>_inst.v (I'm using verilog) file. I am running Ubuntu 16.04 and I executed $find . -name "*inst*"
There are 0 files in my project directory or any subdirectories with the string "inst" in the name.
3.)
While I have a design on the Cyclone V, I would expect one of the 3 indicator LEDs for the Ethernet connection speed to be lit, but all are dim. In my case, the board is connected properly through the Ethernet port (It shows the 100 megabit LED as lit with the factory default image and I have used the Board Update Portal in the past).
If possible, could you explain what I should connect these LEDs to? Or tell me if this sounds as though something is invalid? I don't know how much Quartus can do automatically. I just tried to instantiate the module in my project's top level verilog file (without any of my own logic) based on what I saw from the top level verilog file auto generated with the triple speed Ethernet IP.
Here's some information about my setup. Let me know if there is something else you need.
IP core: Triple-Speed Ethernet Intel FPGA IP
Variation: 10/100/1000Mb Ethernet Mac with 1000 BASE-X/SGMII PCS
All Other Parameters: EVERYTHING IS THE DEFAULT
Distribution: Ubuntu 16.04
Quartus Prime Version: 18.0
FPGA Board: Cyclone V GT Development Kit
Programming Method: USB Blaster II
Best Regards, Alex