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Altera_Forum's avatar
Altera_Forum
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11 years ago

Help with Cyclone V Transceiver Native PHY IP Core

Hello, I am trying to wrap my head around the workings of the Cyclone V Transceiver Native PHY IP Core. I have been reading documentation and I understand there three modules that required: Transceiver PHY, Transceiver Reconfig Controller, and the PHY Reset Controller. My plans are not to use a NIOS processor to interface with the core, it will be HDL code. My first question is what is the indicator that data has been received and is ready to be read from the IP core? Is there some output pin on the core that I can poll?

Last, does anyone know of an example that can help me get going? This transceiver will interface with a Fiber SFP+ Transceiver. I have set the Standard PSC mode to BASIC. If anyone can help me get going that would be fantastic.

Thanks,

joe

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi, I have managed to get a small design working. I have set the Native Core for 8B/10B mode and I am using the tx_datak port to put the link in Control mode or Data Mode. I am also using 8B/10B Control Groups [K28.5, K5.6] for IDLE mode. Groups [K23.7, K23.7] for Carrier Extend mode. My transceiver will connect to a Fiber Transceiver SFP+ module. I'm making progress but have a problem with the received data. In my testbench connect the transmit serial data into the receiver serial data port. I am able to transmit a 16-bit count and I am receiving the data, but I am missing some count values.

    I will attach my archived design and a screen shot.

    If anyone has some experience with transceivers can you please look over what I have and run an Gate Level sim.

    Thanks,

    joe
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi, I have found my problem with the transceiver. I had to connect the tx_std_clkout port on the transceiver to the tx_std_coreclkin pin and the rx_std_clkout to the rx_std_coreclkin pin on the transceiver. Also, the tx_std_clkout should drive the transmit data. I'll upload my design. I thank David and Jerry from Altera for all their help.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Would it be possible to re-send the complete image. I am new to transceiver on Cyclone V GX.

    This would help me to understand how to wire-up the modules together..

    Thanks.

    Regards,

    CS
  • SethuramS's avatar
    SethuramS
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hi all, Does anyone know Cyclone V Transceiver Native PHY IP Core configuration for the above queries. I'm also working with a Fiber SFP+ Transceiver. I have a problem with the receiving data, only one corrupted packet in a set of packets (00 to FF).

    Like, I have to send (00 to FF)-225 packets in that, one packet has 78 bytes (with a header, data[72bytes], checksum[1byte], tailer[1byte]).

    Example packet:

    5AA548 0202020202020202020202020202020202020202020202020202020202020202020202020 2020202020202020202020202020202020202020202020202020202020202020202020202 DA AA