Honored Contributor
Honored Contributornone of the pictures you posted look alright to me. I was expecting two symmetrical lines (well apart) and more towards the edges than the centre.
your frequencies are close to 1 Khz so the lines should be close to location +1 out of x axis from 0 to 4, -4 to 0: ......|.....................................|..... 0....1....2....3....4....-3.....-2....-1....0 if you centre the fft on dc(which I guess you don't) it becomes: ......................|...........|.................. -4....-3....-2....-1....0....1.....2.....3....4 your truncation of 29 bits by taking bit 19:12 is not clear to me. You should be taking the value from MSBs. unless they are "dead" bits i.e. never used by result(indicating low input swing or bad design) your ADC Fs and FFT Fs must be identical, preferably same clock line, else the two clocks must be equal , related and locked to each other. In any case of data and clk acquired from outside then I will use that same clk and I will also check for any timing problems at the io registers which is not normally part of fpga timing report. edit: Your picture indicate some high frequencies near 4KH and this is maximum for your fft, possibly due to some flipping of data. another issue that popped up now is the way you display on the monitor. You must latch your fft output while refrshing the monitor otherwise a free running fft will not give identical block data unless you work hard to do that
