Hi,
I have a working sdram vhdl controller. But it is meant for the device MT48LC2M32B. It is too big and involved and was used for some deep interleaving. I chopped off to leave a demo which may/may not work but should give you some idea about sdram in general.
The demo module writes 128 bits of input data to sdram which has a 32bit bus,then reads it back. It needs row/column address as input to control the functionality as required. The sdram module must be fast enough to accomodate all states of the design per data clock cycle. The sdram clock and data clock domains must be related(153.6/8.53333... = 18 exactly)
You will need to get the datasheet for above device to understand the vhdl.
edit:you also need to connect the sdram datain/out to the one bidirectional bus. For readability I left the correct row/column addressing to you.