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Altera_Forum's avatar
Altera_Forum
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15 years ago

help: the DDR2 controller works incorrectly

I use the DDR2 SDRAM Controller v9.1(not the high performance) and my memory is MT47H32M16cc-3. The parameters are set as follows: clock speed 150MHz Data bus width 16bit local width 32bit Row...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Hi,

What FPGA are you compiling for?

In the v10.1 controller there is a TCL script you have to run to make the appropriate IO and timing settings, did you run something like this

You're zip file seems to be empty, if you post the files I can take a look at them..

Grtz,

Olaf

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thank you very much for your help. My FPGA is StratixII EP2S90F1020C3. I don't run any tcl for the project actually, I will try your suggestion. The attached file just contains one SignalTap file and one design file, not the whole project. I will change it.

Thanks again.