Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

help: the DDR2 controller works incorrectly

I use the DDR2 SDRAM Controller v9.1(not the high performance) and my memory is MT47H32M16cc-3. The parameters are set as follows: clock speed 150MHz Data bus width 16bit local width 32bit Row...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

What FPGA are you compiling for?

In the v10.1 controller there is a TCL script you have to run to make the appropriate IO and timing settings, did you run something like this?

Maybe it's related to the following issue:

http://www.altera.com/support/kdb/solutions/rd12132010_638.html

You're zip file seems to be empty, if you post the files I can take a look at them..

Grtz,

Olaf