Honored Contributor
Honored ContributorHi Jake,
Thanks for the letter. I already defined, and in the middle of writing in Verilog stage No. 1: the interface (communications) between the external controller and my FPGA. It's a set of registers (data to write, chunk length, because the bytes are written in chunks, session trigger register etc.). Basically, every time I'm about to write a byte, the controller writes me the next byte, inside my FPGA, and I'm in the middle of writing the interface to the external controller, thta will alaso communicate with the controller to the CFI Flash. What I miss is some guidance for stage 2: the controller that handles the writings to the CFI Flash. I have some questions regarding this controller: 1. There are some commands in the Intel Flash (suspende, erase, program...). Which commands do I have to implement? 2. I saw the 'program' command, but it says in the datasheet that it's comprised of two cycles. The first cycle is the address writing but the data bus, during the address writing, is supposed to hold one of two values: 10/ 40. Which value do I have to put on the data bus: 10 or 40 (I'm relating to the Intel StartaFlash)? 3. Is this a simple state-machine, because I recall that in the Flash writing there is some algorithm running to make sure the right data was written to the right address. Do I have to implement that algorithm? 4. Are there any indications/ alarms you can recommend me to put in my deisgn to make this state machine more efficient? Is there a reference design to this, since I don't have a NIOS system. Thanks for the attention. Best Regards, Eldad Fargon
