Help needed with DDR2 High Performance Core

Hey everyone,

I am currently having trouble trying to simulate the DDR2 High Performance Controller. And worst of all is that I don't know how to proceed.

A bit of a background. I am working with a Stratix II GX device, and am using Quartus 9.0. In my current design we are using the old legacy DDR2 Controller. I've had no trouble simulating this module so far.

However trying to put in the DDR2 High Performance Controller in a simulation environment is proving to be almost impossible. To start with, the IP Functional Model generated by Quartus does not have the same pins as the actual core. The functional model contains control_* signals and I am not sure what is the purpose of those. Furthermore, the model does not contain any ddr_dq, ddr_dqs or ddr_dm signals.

I have tried to find information on simulation problems with this core, but most people seem to have no problems. Any suggestions what i need to do to simulate this core?

Any help would be greatly appreciated.

Martin