Help needed: clock video input issues early endofpacket

Thanks Jake and Vgs for the reply.

The clocked video input FIFO is set large enough.

And before trying with no buffering BOB, i was using deinterlacing with triple buffering as in my actual design, i need motion adaptive deinterlacing.

And thus, with buffering in deinterlacer as well, the same problem persists.

The board which we are using, doesn't have any reference design for video and this is the first time we have to implement a video pipeline on this board.

BTW, the clock frequency for the altera VIP IPs is 100 Mhz and DDR2 is configured on half-rate mode. and the frame buffer / deinterlacer masters access the memory at 83.5 MHZ as the DDR2 is run at 167 Mhz, which works fine on the other development boards i have worked on.

and what i want to know is, if all the following combination doesn't work on this board, how can i find out what could be the actual problem, in the sense how do i debug..

1. Clock video Input --> Color plane sequencer --> chroma re-sampler --> color space converter --> de-interlacer (triple buffering) --> scaler --> custom component

2. Clock video Input --> Color plane sequencer --> chroma re-sampler --> color space converter --> de-interlacer (no buffering) --> scaler --> frame buffer (triple buffering) --> custom component

and there r few more such combinations, which doesnt work and the problem remains there.

I would need triple buffering in the pipeline as the output frame rate is not same as input frame rate.

Also, i can get a few full frames, lets say for around a minute, i can see the full frame video but slowly the frame becomes smaller and smaller with early EOP shifting its place, with lesser and lesser pixels appear in the output.

And i suspect it is not a video pipeline design / clock problem. But i suspect the memory has some issue but i don't know how to debug and catch the problem.

any suggestions about this would be of great help.

Thanks.