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Altera_Forum
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16 years ago

Help needed: clock video input issues early endofpacket

Hi, We have a design to implement which uses the Altera VIP suit IPs and on quartus 8.0 , on cyclone 3c120 FPGA. the video pipeline is as follows. clock video input --> color plane se...
Altera_Forum's avatar
Altera_Forum
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16 years ago

You get the early endofpacket when the FIFO in the clocked video input overflows. This is obviously caused by the downstream components not pulling the data out fast enough. You need to calculate how fast to run the video IP to allow the deinterlacer to perform it's line duplication without overflowing the upstream buffer in the clocked video input.

Jake