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Altera_Forum
Honored Contributor
Honored ContributorHelp needed: clock video input issues early endofpacket
Hi, We have a design to implement which uses the Altera VIP suit IPs and on quartus 8.0 , on cyclone 3c120 FPGA. the video pipeline is as follows. clock video input --> color plane se...
Altera_ForumHonored Contributor
Honored ContributorHi,
I believe you may be having an issue because of the deinterlacer. When using bob without buffering, the input rate of the deinterlacer is halved because there are two lines going out for each input lines going in. In practice, this means that the deinterlacer applies back pressure for one line after each line received. If the output rate of the clocked video input (number of valid cycles assuming ready remains high) is under 50% then I think you will be able to solve the problem by increasing the buffering in the clocked video input. Otherwise you may be able to increase the clock frequency of your datapath to go below this 50% limit. You may also want to try using bob with double or triple buffering and perhaps even remove the frame buffer in the later case.
