Honored Contributor
Honored ContributorOk I've checked your design and it's a bit more complicated than I first thought.
With the current blocks in your design, it is not possible to set the bit width explicitly. The Gain block has bit width parameters, but these control the width of the multiplicand and not the output which is still inferred. To break this loop, you will need to insert a new block: Go to the library browser. Select Altera DSP Builder Blockset -> IO & Bus -> AltBus. Drag this block to your design and put it between "Parallel Adder Subtractor1" and "Delay". Double click on the new block and set its type and bit width. Now when you run you will get a new error, this is because you have connected the DSPB "Single Pulse" block to the input port of a "Input" block. This is not directly allowed (there are ways around it but probably best ignored for now) and instead you should use a source from the main simulink library. I would strongly recommend reading the DSPB documentation and working through the tutorials. Hope that helps!
