JLee25
Contributor
ContributorHDMI Reference Design FR_CLK
Hi all,
I am curious to know the requirement of this fr_clk mentioned in C10 GX HDMI UG, https://www.intel.com/content/www/us/en/programmable/documentation/ezu1511767661589.html.
My question i...
HI Johnson,
On 2nd thought, I think you can still connect fr_clk while providing whatever clk frequency that's available on your board. Eg : 100MHz.
I found out more info. It should still works as stated from below A10 HDMI example design guideline doc that explained on fr_clk functionality.
- Free running clock (625 MHz) for primary transceiver reference clock. This clock is required for transceiver calibration during power-up state. This clock can be of any frequency.
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-hdmi-de.pdf
Thanks.
Regards,
dlim
