HDMI Long Lock Time

Hi Johnson,

May I know are you using Intel HDMI IP or your own HDMI IP ?

• So far, I am only aware of one slow lock time issue on Intel HDMI IP but that issue is only affecting Stratix 10 FPGA, not Cyclone 10 FPGA. Anyway, the issue has been fixed since QUartus Pro v18.0.1
• https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2018/why-does-stratix-10-hdmi-design-example-rx-lock-time-is-longer--.html

Are you referring to Intel HDMI sink "locked" or "vid_lock" issue ? Some lock scenario example as below.

• Have you ensure you are sending all valid HDMI data ?
• If user is sending invalid control data, then the LOCKED port from the HDMI RX core will be deasserted.
• If user is sending valid control data, but invalid Data Island, then they will see LOCKED port asserted but VID_LOCK deasserted.
• locked [2:0] should have 3 bits. Do you see different result within these 3 bits ?
• Does upgrading to latest Quartus version helps to resolve issue ?

Have you isolate the issue to find out under what operating condition that you observe slow lock time ?

• Like does it has dependency on certain video resolution change ?
• Does reducing video resolution helps to see if this issue is related to signal integrity concern ?

Finally, have you isolated whether the bottleneck resides in HDMI IP, or PLL or transceiver channel ?

• Did you probe PLL lock, transceiver CDR lock or rx_ready signal and compare with HDMI lock status ?

Thanks.

Regards,

dlim

Hi Dlim,

Thanks for getting back.

I am using Intel HDMI IP and the the long lock issue was mentioned on,

https://www.intel.com/content/www/us/en/programmable/documentation/ezu1511767661589.html

I noticed this in my latest compilation resolution, same hardware and same source...

In my previous test, there's no long lock issue..

FYI!

BRs,

Johnson

Hi Johnson,

Thanks for pointing out the long lock time limitation in C10 GX HDMI design example doc.

I want to clarify further with you first before I check with Intel Engineering team on long lock time issue fix update.

• May I know are you using just HDMI IP or HDMI design example that encounter this long lock time issue ?
• V19.2 : you countered long lock time issue
• You also mentioned previous Quartus version doesn't face this issue. Can you let me know which previous Quartus version is working fine ?

Thanks.

Regards,

dlim

Hi Dlim,

For this issue, I am using HDMI IP on custom board and Quartus Pro V19.2.

I used to test HDMI reference design on C10 GX EVB, Q18.0.1..

I am asking because I noticed the Rx is always work with 1080p but not UHD...

And I want to clarify this issue is coming form the IP or Signal Integrity.

Thank you!

BRs,

Johnson

Hi Johnson,

Ok, thanks for providing more info but let's not mix up the 2 issues here.

1. Regarding UHD is not working issue

• There are a lot of factor that may impact the functionality like Quartus design timing closure, board signal_integrity, transceiver link tuning and etc
  • You need to slowly isolate the issue first

1. Regarding HDMI slow lock time issue

• For this, I have clarified with Intel Engineering team. I get a better understanding now and sorry for the confusing design limitation write up in the HDMI design example doc
  • What the attached design example statement screen shot means is
    • using HDMI IP only, it won’t achieve fast lock time
    • As a workaround, user can follow HDMI design example to use the symbol_aligner.v design to improve the lock time.

Thanks.

Regards,

dlim