HDMI Long Lock Time

Hi Johnson,

May I know are you using Intel HDMI IP or your own HDMI IP ?

• So far, I am only aware of one slow lock time issue on Intel HDMI IP but that issue is only affecting Stratix 10 FPGA, not Cyclone 10 FPGA. Anyway, the issue has been fixed since QUartus Pro v18.0.1
• https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2018/why-does-stratix-10-hdmi-design-example-rx-lock-time-is-longer--.html

Are you referring to Intel HDMI sink "locked" or "vid_lock" issue ? Some lock scenario example as below.

• Have you ensure you are sending all valid HDMI data ?
• If user is sending invalid control data, then the LOCKED port from the HDMI RX core will be deasserted.
• If user is sending valid control data, but invalid Data Island, then they will see LOCKED port asserted but VID_LOCK deasserted.
• locked [2:0] should have 3 bits. Do you see different result within these 3 bits ?
• Does upgrading to latest Quartus version helps to resolve issue ?

Have you isolate the issue to find out under what operating condition that you observe slow lock time ?

• Like does it has dependency on certain video resolution change ?
• Does reducing video resolution helps to see if this issue is related to signal integrity concern ?

Finally, have you isolated whether the bottleneck resides in HDMI IP, or PLL or transceiver channel ?

• Did you probe PLL lock, transceiver CDR lock or rx_ready signal and compare with HDMI lock status ?

Thanks.

Regards,

dlim