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amildm's avatar
amildm
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3 years ago
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HDMI IP -> DRMI (Dynamic Range Mastering InfoFrame) -> how to derive?

Hi,

In the HDMI Sink, the DRMI packets are mapped to the Address 0x88 of the Auxiliary Packet Memory Map:

https://www.intel.com/content/www/us/en/docs/programmable/683798/22-1-19-7-0/sink-auxiliary-data-port.html

But, how can I send the DRMI packets through the HDMI source? What's port should be used?

Thank you!

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  • amildm's avatar
    amildm
    Icon for Contributor rankContributor
    3 years ago

    I'm going to test the proposed configuration on the board till end of the week, so meanwhile please don't close the case, thanks!

  • ZH_Intel's avatar
    ZH_Intel
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    3 years ago

    Hi amildm,

    Thank you for the update.

    >Should anything else be changed in the RTL in order to pass through the original DRMI frames with

    >the original HDR metadata?

    I have check with our internal team on this.

    You may need to set multiplexer_in0_valid of the avalon_st_multiplexer instance in the altera_hdmi_aux_hdr.v file to 1'b0 to prevent the Auxiliary Packet Generator from forming and inserting additional HDR InfoFrame into the TX Auxiliary stream.

    You may refer to below link for more information:

    HDMI Intel® FPGA IP Design Example User Guide - Disabling HDR Insertion and Filtering

    Best Regards,

    ZulsyafiqH_Intel

    • amildm's avatar
      amildm
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      3 years ago

      You are referring to the Design Example for Arria 10, but I'm working with the Cyclone-10.

      Instructions for Cyclone 10 DRMI Filtering are different:

      https://www.intel.com/content/www/us/en/docs/programmable/683309/21-1-19-6-0/dynamic-range-and-mastering-hdr-infoframe.html

      but they are not compatible with the generated code...

      The User Guide for Arria 10, which you are referring to, is compatible to the generated code, which I have in my project...

      Anyway, I'll set the multiplexer_in0_valid signal to '0' according to your recommendation and let you know whether it works.

      • amildm's avatar
        amildm
        Icon for Contributor rankContributor
        3 years ago

        I've checked the modified design on the board - it works! Thanks a lot for your support, please close the case for now ...

  • ZH_Intel's avatar
    ZH_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    3 years ago

    Hi amildm,

    Thank you for the update.

    Yes, you are correct, we have already issue a fix to update the design example user guide.

    The update is scheduled to be fixed in the next release of the HDMI Intel® Cyclone 10 GX FGPA IP Design Example User Guide.


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


    Thank you.


    Best Regards,

    ZulsyafiqH_Intel