Forum Discussion
ContributorHDMI IP -> DRMI (Dynamic Range Mastering InfoFrame) -> how to derive?
You are referring to the Design Example for Arria 10, but I'm working with the Cyclone-10.
Instructions for Cyclone 10 DRMI Filtering are different:
but they are not compatible with the generated code...
The User Guide for Arria 10, which you are referring to, is compatible to the generated code, which I have in my project...
Anyway, I'll set the multiplexer_in0_valid signal to '0' according to your recommendation and let you know whether it works.
Frequent ContributorHi amildm,
Thank you for the update.
>Should anything else be changed in the RTL in order to pass through the original DRMI frames with
>the original HDR metadata?
I have check with our internal team on this.
You may need to set multiplexer_in0_valid of the avalon_st_multiplexer instance in the altera_hdmi_aux_hdr.v file to 1'b0 to prevent the Auxiliary Packet Generator from forming and inserting additional HDR InfoFrame into the TX Auxiliary stream.
You may refer to below link for more information:
HDMI Intel® FPGA IP Design Example User Guide - Disabling HDR Insertion and Filtering
Best Regards,
ZulsyafiqH_Intel
ContributorYou are referring to the Design Example for Arria 10, but I'm working with the Cyclone-10.
Instructions for Cyclone 10 DRMI Filtering are different:
but they are not compatible with the generated code...
The User Guide for Arria 10, which you are referring to, is compatible to the generated code, which I have in my project...
Anyway, I'll set the multiplexer_in0_valid signal to '0' according to your recommendation and let you know whether it works.
- amildm
I've checked the modified design on the board - it works! Thanks a lot for your support, please close the case for now ...
