HDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro

Hi Wincent_Altera,

Thanks for the project file .qar.

I unpacked the files, and looked at the HDMI IP Rx and Tx cores.

Searching for VIDEO_PROTOCOL shows that the setting is "none" for clocked video, and not "vvp_full" for "AXIS-VVP Full"; relevant files are:

• ^/hdmi_0_example_design/rtl/hdmi_rx/hdmi_rx/hdmi_rx.html and .xml
• ^/hdmi_0_example_design/rtl/hdmi_tx/hdmi_tx/hdmi_tx.html and .xml

The design also shows it, since the HDMI IP Rx and Tx PHYs are not used as would require AXIS-VVP Full, but the transceivers for HDMI are made using GXB blocks directly.

May I suggest that you take a look at the original question from December 15 2024, and try to generate the HDMI Core with:
- Direction: Receiver
- Enable Active Video Protocol: AXIS-VVP Full
- Support FRL: Untick (disabled)

The generated design is also attached as a file .qar with the original question.

Simply by code inspection of the generated hdmi_rx_core_altera_hdmi_1975_ozylggi.v file, it is possible to see that there is problem with the design.

The module hdmi_rx_core_altera_hdmi_1975_ozylggi is used in file hdmi_rx_core.vhd at lines 192 forward through a component with configuration as:

...
hdmi_0 : component hdmi_rx_core_altera_hdmi_1975_ozylggi_cmp
generic map (
FAMILY => "Arria 10",
SYMBOLS_PER_CLOCK => 2,
PIXELS_PER_CLOCK => 8,
...

The module in file hdmi_rx_core_altera_hdmi_1975_ozylggi.v has code:

...
wire [SYMBOLS_PER_CLOCK - 1 : 0] cv_vid_de;
...
for (p=0; p<PIXELS_PER_CLOCK; p=p+1) begin: vid_data_p
...
if(cv_vid_de[p] && (vid_valid == 1'b1)) begin
...

So loop variable p is in range 0 to PIXELS_PER_CLOCK - 1 = 8 - 1 = 7, but wire cv_vid_de is only defined with range 0 to SYMBOLS_PER_CLOCK - 1 = 2 - 1 = 1.

During synthesis, Quartus tries to access p[2], that is out of range, thus giving the error meassage:
Error(13224): Verilog HDL or VHDL error at hdmi_rx_core_altera_hdmi_1975_ozylggi.v(771): index 2 is out of range [1:0] for 'cv_vid_de'

This problem can be confirmed by code inspection, thus without any pin placement or other synthesis.

Have you tried to recreate the original problem that I reported, showing the above problem in the code ?

Regards
M_DK_FPGA

Hi Wincent_Altera,

Thanks for the project file .qar.

The HDMI Rx IP shows that the Video Protocol is None, as you can seen in the attached image.

May I suggest that you try to unpack the qar file you attached, and check the actual IP setting.

You can also just search for VIDEO_PROTOCOL in the files, where you in file ^/devkit2/hdmi_0_example_design/rtl/hdmi_rx/hdmi_rx/hdmi_rx.xml will find <parameter name="VIDEO_PROTOCOL" value="none" />.

Please also take a look at the originally generated code, where I in my previous answer described the mismatch between config parameters PIXELS_PER_CLOCK and SYMBOLS_PER_CLOCK.

Also you could try just to run the synthesis of the originally attached qar file, which will shown the problem.

That should be straight forward to do.

Thanks for the offer for a Teams Call

For now I think we have enough technical issues to resolve, so until the above is addressed I would not think a Teams Call is required.

Regards
M_DK_FPGA