Forum Discussion
Occasional ContributorHDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi @M_DK_FPGA ,
I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.Currently AXI Bridge is setting to 16BPS (16x3 48bits).
If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
Detail about the implementation you may refer to- HDMI user guide 5.1.19. AXI4-Stream to Clocked Video Converter (AXI2CV)
- Intel AXI Streaming Video Protocol Specification: 2.2.10. Packing RGB444 onto an RGB888 Interface
Hope that able to help you to move a step forward, let me know if further clarification is needed.
Regards,
Wincent_Altera
Occasional ContributorHi Wincent_Altera,
Thanks for the project file .qar.
The HDMI Rx IP shows that the Video Protocol is None, as you can seen in the attached image.
May I suggest that you try to unpack the qar file you attached, and check the actual IP setting.
You can also just search for VIDEO_PROTOCOL in the files, where you in file ^/devkit2/hdmi_0_example_design/rtl/hdmi_rx/hdmi_rx/hdmi_rx.xml will find <parameter name="VIDEO_PROTOCOL" value="none" />.
Please also take a look at the originally generated code, where I in my previous answer described the mismatch between config parameters PIXELS_PER_CLOCK and SYMBOLS_PER_CLOCK.
Also you could try just to run the synthesis of the originally attached qar file, which will shown the problem.
That should be straight forward to do.
Thanks for the offer for a Teams Call
For now I think we have enough technical issues to resolve, so until the above is addressed I would not think a Teams Call is required.
Regards
M_DK_FPGA
Wincent_AlteraRegular Contributor
Hi,
Using HDMI PHY Intel FPGA IP Design example, it enable the AXIS-VVP-FULL by default.
As per mentioned by Rong Yuan in the past reply.Next will try to disable AUX and deep color and see if I am able to replicate your issue or not.
Regards,Wincent_Altera
- Wincent_Altera
Hi @M_DK_FPGA ,
Sorry forget to update you, try to disable AUX and deep color the AXIS-VVP full by default disable again in new generated HDL.
I might need more time to check on this (around 7-14 days).
Will update you back ASAP.
Regards,
Wincent_Altera- Wincent_Altera
Hi @M_DK_FPGA ,
we need more time to enable this feature, meanwhile do you able to file an IPS case ?
with IPS cases, it can help us to raise the ticket level into higher level.
From the previous reply, seen that you having problem to get that done.
My suggestion is to reach out to the distributor FAE where you got the product from.
They will help to file on behave, just put this Forum link in the description, I will be there to support you.
Regards,
Wincent_Altera
