Forum Discussion
Occasional ContributorHDMI Intel FPGA IP as Receive with AXIS fails in Analysis & Synthesis of Quartus 24.3 Pro
Hi @M_DK_FPGA ,
I understand your reason to turn off the "support Aux" and "deep colour" with reason to support your custom 24 bit pixel data.
However , turning OFF support Aux and deep colour will make the output in-stable (blank most of the time).
Also, This will only save minor logic utilization. That why we make those two as default to suit most of the use cases.Currently AXI Bridge is setting to 16BPS (16x3 48bits).
If fewer bits are requires, you just need to pad the LSB without disable the AUX and Deep Colour.
Detail about the implementation you may refer to- HDMI user guide 5.1.19. AXI4-Stream to Clocked Video Converter (AXI2CV)
- Intel AXI Streaming Video Protocol Specification: 2.2.10. Packing RGB444 onto an RGB888 Interface
Hope that able to help you to move a step forward, let me know if further clarification is needed.
Regards,
Wincent_Altera
Regular ContributorHi,
Using HDMI PHY Intel FPGA IP Design example, it enable the AXIS-VVP-FULL by default.
As per mentioned by Rong Yuan in the past reply.
Next will try to disable AUX and deep color and see if I am able to replicate your issue or not.
Regards,
Wincent_Altera
Regular ContributorHi @M_DK_FPGA ,
Sorry forget to update you, try to disable AUX and deep color the AXIS-VVP full by default disable again in new generated HDL.
I might need more time to check on this (around 7-14 days).
Will update you back ASAP.
Regards,
Wincent_Altera
- Wincent_Altera
Hi @M_DK_FPGA ,
we need more time to enable this feature, meanwhile do you able to file an IPS case ?
with IPS cases, it can help us to raise the ticket level into higher level.
From the previous reply, seen that you having problem to get that done.
My suggestion is to reach out to the distributor FAE where you got the product from.
They will help to file on behave, just put this Forum link in the description, I will be there to support you.
Regards,
Wincent_Altera
M_DK_FPGAHi Wincent_Altera,
Thanks for your feedback, and suggestion about raising an IPS case.
As described previously, then Intel rejected my request for an IPS account, so to make an IPS case I have to go through our FAE, who have offered the possibility through some shared IPS account. However, I am reluctant to draw on the good will of our FAE, just to ask the same question and start yet another lengthy support case in another forum.
During this support case I have provided substantial material that indicates a problem in the HDMI core IP, starting with the initial posting more than 11 weeks ago, but there is no indication that support ever attempted to reproduce these problem, through it would only require synthesis of the uploaded archives, to acknowledge the problem.
Instead I have been offered workarounds, that I dutifully have attempted, and provided replies in a day or two, but when I have pointed out problems with the workaround, my substantial issues and questions have not been addressed.
So as a small company we have been forced to search for another path through with the HDMI core IP, since relaying on support bears the risk of jeopardizing the project.
Regards
M_DK_FPGA- Wincent_Altera
Hi @M_DK_FPGA ,
I was able to replicate your issue as mentioned in 2 March 2025 reply.
try to disable AUX and deep color the AXIS-VVP full by default disable again in new generated HDL.
When remove the deep color at the IP core in Arria 10 in example design generation , we seeing the same error as yours.
I understand your frustration, Please do believe that I am trying my best to ensure your success.
Also, i do understand your concern, I am working with our design team to fix this issue. But the investigation may take longer time.
You can ignore the request to having IPS on this.
I will raise the support level in to higher level, hope we can get some investigation result back soon.
Please accept my apology if for the inconvenience cause to you.
Regards,
Wincent_Altera
