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Altera_Forum's avatar
Altera_Forum
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10 years ago

HDL Import [state machine in VHDL]

Hi everyone, I designed a state machine in VHDL and I would like to incorporate it to my Simulink + DSP Builder Model. I'm using HDL Import, however upon pressing Compile button I get the error...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thank you for the comment and suggestions. The code looks much better.

I can actually compile original code in Quartus as well (no errors/warnings). The problem is importing this code into Simulink model with DSP Builder.