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Altera_Forum's avatar
Altera_Forum
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11 years ago

HDL Import [state machine in VHDL]

Hi everyone, I designed a state machine in VHDL and I would like to incorporate it to my Simulink + DSP Builder Model. I'm using HDL Import, however upon pressing Compile button I get the error...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The source compiles OK with Quartus II 14.1

However the following code is a bit odd to read 

	process(clk_in, init_in, counter)
	begin
		if (rising_edge(clk_in) and init_in = '1') then
			if (counter = 63) then
				counter <= 0;           -- resets counter when it reaches 320
			else
				counter <= counter + 1;
			end if;
		elsif (rising_edge(clk_in) and init_in = '0') then
			counter <= 0;               -- if "init_in" is set to 0, counter resets, as well as "start_tx_out"
		end if;
	end process;

and most would write it like this: 

	process(clk_in)
	begin
		if rising_edge(clk_in) then
			if (init_in = '1') then
				if (counter = 63) then
					counter <= 0;           -- resets counter when it reaches 320
				else
					counter <= counter + 1;
				end if;
			else
				counter <= 0;               -- if "init_in" is set to 0, counter resets, as well as "start_tx_out"
			end if ;
		end if;
	end process;

Both ways seem to generate the same result, though.