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Honored Contributor

10 years ago

HDL Import [state machine in VHDL]

Hi everyone,

I designed a state machine in VHDL and I would like to incorporate it to my Simulink + DSP Builder Model. I'm using HDL Import, however upon pressing Compile button I get the error message shown bellow. Same happens when I try to compile the whole Quartus project.

State machine VHDL is attached to this message.

I would appreciate any hints on how to solve this problem.

Best regards,

Oz

--- Quote Start ---

Generating Simulink model........

Info: *******************************************************************

Info: Running Quartus II 64-Bit Analysis & Synthesis

Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Full

Version

Info: Copyright (C) 1991-2013 Altera Corporation. All rights reserved.

Info: Your use of Altera Corporation's design tools, logic functions

Info: and other software and tools, and its AMPP partner logic

Info: functions, and any output files from any of the foregoing

Info: (including device programming or simulation files), and any

Info: associated documentation or information are expressly subject

Info: to the terms and conditions of the Altera Program License

Info: Subscription Agreement, Altera MegaCore Function License

Info: Agreement, or other applicable license agreement, including,

Info: without limitation, that your use is for the sole purpose of

Info: programming logic devices manufactured by Altera and sold by

Info: Altera or its authorized distributors. Please refer to the

Info: applicable agreement for further details.

Info: Processing started: Sat Mar 28 15:03:10 2015

Info: Command: quartus_map suballoc --source=../../suballoc/suballoc.vhd

--simgen

--simgen_parameter=SIMGEN_C_NETLIST=ON,SIMGEN_OPTIMIZATION=ALL,SIMGEN_PRESERVE_PORT_ORDER=ON

Info (20029): Only one processor detected - disabling parallel compilation

Info (12021): Found 2 design units, including 1 entities, in source file

/primjeri/suballoc/suballoc.vhd

Info (12022): Found design unit 1: suballoc-behavioral

Info (12023): Found entity 1: suballoc

Info (12127): Elaborating entity "suballoc" for the top level hierarchy

Info (281010): Generating sgate simulator netlist using Simgen

SIMGEN_PROGRESS Start of Model generation -- 0% complete

SIMGEN_PROGRESS Phase 1 : Internal Objects created -- 25% complete

SIMGEN_PROGRESS Phase 2 : Connections between internal objects

made -- 60% complete

SIMGEN_PROGRESS Phase 3 : Netlist generated -- 100% complete

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|dataa already has one or more bits in the range 5 to 5 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|datab already has one or more bits in the range 5 to 5 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|outputselect already has one or more bits in the range 5 to 5 assigned.

CAUSE : The port range was already assigned a value. The new value can

not be reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|dataa already has one or more bits in the range 4 to 4 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|datab already has one or more bits in the range 4 to 4 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|outputselect already has one or more bits in the range 4 to 4 assigned.

CAUSE : The port range was already assigned a value. The new value can

not be reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|dataa already has one or more bits in the range 3 to 3 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|datab already has one or more bits in the range 3 to 3 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|outputselect already has one or more bits in the range 3 to 3 assigned.

CAUSE : The port range was already assigned a value. The new value can

not be reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|dataa already has one or more bits in the range 2 to 2 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|datab already has one or more bits in the range 2 to 2 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|outputselect already has one or more bits in the range 2 to 2 assigned.

CAUSE : The port range was already assigned a value. The new value can

not be reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|dataa already has one or more bits in the range 1 to 1 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|datab already has one or more bits in the range 1 to 1 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|outputselect already has one or more bits in the range 1 to 1 assigned.

CAUSE : The port range was already assigned a value. The new value can

not be reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|dataa already has one or more bits in the range 0 to 0 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|datab already has one or more bits in the range 0 to 0 assigned. CAUSE :

The port range was already assigned a value. The new value can not be

reassigned.

Error (281011): MGL_INTERNAL_ERROR: The source port simgen|mux21 inst nl|outputselect already has one or more bits in the range 0 to 0 assigned.

CAUSE : The port range was already assigned a value. The new value can

not be reassigned.

Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 18 errors,

0 warnings

Error: Peak virtual memory: 519 megabytes

Error: Processing ended: Sat Mar 28 15:03:12 2015

Error: Elapsed time: 00:00:02

Error: Total CPU time (on all processors): 00:00:02

Error: Quartus II Analysis & Synthesis was unsuccessful

--- Quote End ---

suballoc.vhd3 KB

2 Replies

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Honored Contributor

The source compiles OK with Quartus II 14.1

However the following code is a bit odd to read

	process(clk_in, init_in, counter)
	begin
		if (rising_edge(clk_in) and init_in = '1') then
			if (counter = 63) then
				counter <= 0;           -- resets counter when it reaches 320
			else
				counter <= counter + 1;
			end if;
		elsif (rising_edge(clk_in) and init_in = '0') then
			counter <= 0;               -- if "init_in" is set to 0, counter resets, as well as "start_tx_out"
		end if;
	end process;

and most would write it like this:

	process(clk_in)
	begin
		if rising_edge(clk_in) then
			if (init_in = '1') then
				if (counter = 63) then
					counter <= 0;           -- resets counter when it reaches 320
				else
					counter <= counter + 1;
				end if;
			else
				counter <= 0;               -- if "init_in" is set to 0, counter resets, as well as "start_tx_out"
			end if ;
		end if;
	end process;

Both ways seem to generate the same result, though.

Altera_Forum
Honored Contributor
10 years ago
Thank you for the comment and suggestions. The code looks much better.

I can actually compile original code in Quartus as well (no errors/warnings). The problem is importing this code into Simulink model with DSP Builder.