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Altera_Forum
Honored Contributor
Honored ContributorHDL import - Multiple clock error
Hi, I was trying to convert the DE2 i2sound example (found in the DE2 demonstrations) to a DSP builder model file using HDL import technique. But i'm having a problem with multiple clocks ( 2 inte...
Altera_ForumHonored Contributor
Honored ContributorHi Onee,
Did you simulate your HDL codes? According to your *.fit.summary report file, your design consists of only 2 registers. Many warning messages are reported in *.map.rpt informing most of registers are reduced due to stuck clock or clock enable. EOFZ
