HDL import - Multiple clock error

Hello everyone,

I think i've solved the multiple clock related problem. As far as i've understood, if your verilog code has more than one signals whose edges triggers different events then in HDL import block, all these inputs are considered as clocks and the software tries to reduce them into a single clock. I think i've solve this problem in my code, i've now used only one clock and used logical operations to make the other clocks work.

Now i have only one problem. I've checked all the pins, inputs and outputs and the logic, but i don't know why my design is still not working :( I've only tried to implement a reduced form of the DE2_sound demonstration provided with the board.

Here is my files. Please help.......

thanks.