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Altera_Forum
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14 years ago

HD SDI and Clocked Video Input issues

I'm having trouble integrating an HD SDI transceiver into my existing Stratix IV GX video design. I've ended up stripping it down to a single video path and integrating in the AN600 design to debug the issues, but I'm still unable to get valid video through the system.

My SOPC system is as follows:

CVI -> CRS -> CSC -> Deint (Bob, no buffering) -> CPR (parallel -> serial) -> Clipper (no clipping) -> Scaler (1920x1080 to 640x480) -> VFB (triple buffer) -> CPR (serial -> parallel) -> CVO

The conversion from parallel to serial and vise versa is an artifact of the pre-existing design. The clipper is currently software configurable but not clipping any of the frame.

I have the AN600 Rx-only transceiver driving the CVI. I have the Tx-only transceiver with the test pattern generator hard coded for HD SDI (tx_std = "01"). Using SignalSpy, I can see the data port on the Tx and the Rx sides and everything looks good. I'm seeing valid Vsync, Hsync and Field flags and the Rx_status is 0x01D indicating it has achieved PLL, alignment, TRS and Frame lock.

Looking at the CVI using SignalSpy, I'm seeing the overflow flag set constantly. I'm seeing valid Vsync, Hsync and Field flags. The active_line_count_f0 is 0x0C48 and active_line_count_f1 is 0x0439?? The total_line_count_f0 is 0x0465 and total_line_count_f1 is 0x0467. total_sample_count is 0x1131?? The CVI internal locked flag periodically deasserts for a full video line period.

When I configured the Clocked Video Input module, I used the SDI 1080i60 preset.

Does anyone have any input on what could be wrong here? Any advice on what to look at?

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    So the simulation looked great and I just couldn't figure out why on earth it wasn't working on the board. I've been having problems with the smart recompile not actually "taking" updates so I blew away the db folder and rebuilt. It worked. <sigh>

    On another note, I'm pretty sure serializing the 1080p30 stream is a problem. HD SDI with 2200 samples per line @ 74.25MHz is a line rate of ~29.63us and a frame rate of 33.33us. To maintain that line rate but serializing the data stream, that gives us 6600 samples per line at that 29.63us line rate. That gives a minimum core clock rate of 222.75MHz.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    cvo, needs two clocks, one at the rate of the system, one at the output clock rate of the video system . if the video clock is to slow, or the cvo buffer to small, then you will drop frames. back pressure signals will look like a clock..

    if the output clock is not syncronous / or the cvo has wrong h or v sync, then the video will rip,

    sounds as if you might have both of these..