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Altera_Forum's avatar
Altera_Forum
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14 years ago

HD SDI and Clocked Video Input issues

I'm having trouble integrating an HD SDI transceiver into my existing Stratix IV GX video design. I've ended up stripping it down to a single video path and integrating in the AN600 design to debug ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

So the simulation looked great and I just couldn't figure out why on earth it wasn't working on the board. I've been having problems with the smart recompile not actually "taking" updates so I blew away the db folder and rebuilt. It worked. <sigh>

On another note, I'm pretty sure serializing the 1080p30 stream is a problem. HD SDI with 2200 samples per line @ 74.25MHz is a line rate of ~29.63us and a frame rate of 33.33us. To maintain that line rate but serializing the data stream, that gives us 6600 samples per line at that 29.63us line rate. That gives a minimum core clock rate of 222.75MHz.