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Altera_Forum's avatar
Altera_Forum
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14 years ago

HD SDI and Clocked Video Input issues

I'm having trouble integrating an HD SDI transceiver into my existing Stratix IV GX video design. I've ended up stripping it down to a single video path and integrating in the AN600 design to debug ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Nope, not yet.

I had to spend some time getting the simulation up and running properly. It's running now, albeit rather slowly. At ~3ms in, I'm not seeing any problems yet. I'm not seeing the CVI overflow and all of the Avalon ST handshaking is looking good. It appears to have plenty of bandwidth in that clock domain, especially now that it's running at 200MHz.

I have another build running in Quartus to test it in the hardware again.