Honored Contributor
Honored ContributorSo that didn't completely fix the problem. The Avalon ST ready signals now look like a clock with a 70-30 duty cycle and the video still looks like 3 sets of color bars across with the scrolling zig zag.
I've moved the frame buffer between the CVI and the CRS to see if I can at least get a full frame buffered. Interestingly, the UDX4.1 reference design uses a 148.5MHz video core clock with the following video pipeline: CVI -> AFD Extractor -> Switch -> Clip -> Snoop -> MA Deint -> AFD Clip -> Scaler II -> VFB -> CRS -> CSC -> ........ There has to be something else up in my system. I'm going to work on getting a sim up and running.
